The present invention relates to computer architecture and, more specifically, to prefetch processes for accessing cache in a computer.
In processing systems such as computers, the data to be utilized by a processor is stored in a memory (e.g., main memory, lower level memory, where lower level cache/memory is deemed closer to the processor and higher level cache/memory levels are deemed further away from the processor) and control logic manages the transfer of data between the memory and the processor in response to requests issued by the processor. The data stored in the main memory generally includes both instructions to be executed by the processor and data to be operated on by the processor. For simplicity, both instructions and operand data are referred to collectively herein as “data” unless the context requires otherwise. The time taken by a main memory access is relatively long in relation to the operating speeds of modern processors. To address this, a cache memory with a shorter access time is generally interposed between the main memory and the processor, and the control logic manages the storage of data retrieved from the main memory in the cache and the supply of data from the cache to the processor.
In embodiments, a cache is organized into multiple data units, such as “lines”, each line providing storage for bits of data from the main memory which may be many bytes in length. When the processor issues a request for data contained in a particular line in a page, or block, of main memory, the control logic determines whether that line is stored in the cache. If the line is stored in cache (i.e., there is a cache hit), the data is retrieved from the cache. If the line is not stored in cache (i.e., there is a cache miss), the data is retrieved from the main memory and the processor's operations dependent on this cache access are stalled while this operation takes place. Since a cache access is much faster than a lower level memory access, it is desirable to manage the system so as to achieve a high ratio of cache hits to cache misses. In some embodiments, multiple levels of cache are provided, where if a cache miss occurs on a first level, the processor attempts to retrieve data from a second level before accessing the main memory. In such embodiments, cache misses occur each time a line is not present in a given cache level, thus also resulting in a performance degradation.